The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 1993
Filed:
Oct. 17, 1991
Taiji Imazu, Itami, JP;
Masao Takiguchi, Itami, JP;
Satoshi Matsumoto, Itami, JP;
Kazuharu Nishitani, Itami, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
In order to obtain an output circuit having pullup resistance which feeds no through current to a CMOS inverter even if output impedance of a front stage circuit is in an extremely high state, an input end and an output end of an inverter (G1) are connected to an input terminal (P.sub.i) and a first input end of an AND gate (G5) respectively. A pulse generation circuit (SG) and a gate of a pullup transistor (Q.sub.1) are connected to a second input end and an output end of the AND gate (G5) respectively. The pullup transistor (Q.sub.1) has a drain and a source which are connected to the input terminal (P.sub.i) and a power source (V.sub.DD) respectively. An input end of a CMOS inverter (11) is connected to the input terminal (P.sub.i). Even if the front stage output impedance is extremely increased after the potential of the input terminal (P.sub.i) has been at a low logical level, the pullup transistor (Q.sub.1) is quickly driven by pulses generated by the pulse generation circuit (SG), to increase the potential of the input end of the inverter (11).