The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 1993

Filed:

Jan. 31, 1992
Applicant:
Inventors:

Katsuyoshi Suzuki, Hadano, JP;

Tatsuki Ishii, Tokyo, JP;

Tomio Taniguchi, Yokohama, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 51 ; 437195 ; 257499 ;
Abstract

A novel wiring method for multilayered semiconductor integrated circuits is disclosed. For example, a semiconductor integrated circuit of a 6-layered wiring structure can be formed with a first layer covered with gates, a second layer, a third layer, a fourth layer and a fifth layer making up logic wiring layers, and a sixth layer making up a power layer. Lattice-shaped wires are formed in a longitudinal direction on the second layer and the fourth layer, and in a lateral direction on the third layer and the fifth layer. The second layer forming the bottom layer and the fifth layer forming the uppermost layer, or a combination of the second layer and the fifth layer of a general wiring structure are used as main layers of wires requiring consideration of signal transmission delay time.


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