P-well cmos process using neutron activated doped n-/n+ silicon

Abstract

About 6 to 20 micrometer resistivity N- (600 ohm-cm and above) silicon is epitaxially deposited on N+ (0.01 to 0.1 ohm-cm) substrates. The resistivity of the epitaxial layer is lowered to 5 to 60 ohm-cm using neutron activated doping. A 1 micrometer p-well process is utilized to build natural (unadjusted) PMOS transistors in the bulk silicon. These transistors operate in the subthreshold region where the threshold or turn on voltages have to match closely across a large device. N-channel transistors are fabricated in a P-well. The advantage of using neutron activated doped silicon is that the carrier concentration is very uniform and therefore threshold variations are much smaller than in transistors built in conventional doped silicon. The use of a neutron doped epitaxial layer on a P-well CMOS process provides a novel approach to control dopant uniformity and thus uniform transistor characteristics as well as providing a heavily doped conventional substrate to enhance resistance to CMOS latch-up.