Dual dielectric field effect transistors for protected gate structures

Abstract

A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electrical and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield. As display sizes increase, the yield problem becomes more and more significant, generally growing as the square of the diagonal measurement of the screen. The structure in the present invention also significantly reduces gate leakage current. In the process and structure of the present invention, gate electrode material is separated from semiconductor material by the aforementioned dual dielectric, typically comprising layers of silicon oxide disposed beneath a layer of silicon nitride which is, in turn, disposed beneath the active amorphous silicon semiconductor material.