The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 1993

Filed:

May. 02, 1991
Applicant:
Inventor:

Kuniyoshi Yoshikawa, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 43 ; 437 30 ; 437 44 ; 437978 ;
Abstract

A method of manufacturing a floating gate type nonvolatile memory cell having an offset region, wherein the length of the offset region is defined by the portion of the substrate covered by the injection blocking film formed on the side wall of the floating gate electrode. Thus, the offset region is self-aligned with respect to the side wall of the floating gate electrode. Moreover, since the insulating film formed on the floating gate electrode includes a nitride film, it is damaged little while the injection blocking film is being formed on or removed from the side wall of the floating gate electrode. In addition, when an oxide film is formed on the offset region, substantially no additional oxide film is formed on the nitride film in the insulating film on the floating gate electrode, and the thickness of the insulating film does not change.


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