Symbol synchronizer for sampled signals

Abstract

A symbol synchronizer derives a symbol clock reference from a sampled baseband signal which may be of a variety of suitable digital signalling formats, including non-return-to-zero (NRZ) and Manchester formats. A one-bit quantizer receives the sampled signal and provides a binary representation thereof to a level-transition detector which generates a sequence of pulses at the symbol rate of the binary-valued data sequence and at a predetermined timing offset from the symbol timing epochs of the data sequence. The timing offset depends on the digital signalling format and is on the interval ##EQU1## where T is the symbol period. The level-transition detector employs delay circuitry, logic circuitry, and a monostable multivibrator to mask transitions in the quantized data sequence that do not occur at the predetermined timing offset from the timing epochs and to generate the symbol clock pulse sequence. The output pulse sequence from the level-transition detector is applied to a binary-quantized digital phase-locked loop (DPLL) which functions to stabilize the data-derived symbol clock. The average pull-in time of the digital phase-locked loop is reduced by the incorporation of a synchronization acquisition aid which automatically pulls the DPLL into synchronization if the estimated symbol clock timing epoch lies within a lock window a predetermined number of times.