Fast store-through cache memory

Abstract

A fast store-through cache process is disclosed in connection with multiple processors sharing a main storage memory. Each processor has a cache memory including multiple cache lines, each line associated with an address in main storage. Each cache memory has a cache directory for recording main storage addresses mapped into cache memory, identifying cache lines as valid or invalid, and holding status bits of data words stored in the cache memory. According to the process, a data word is stored in the cache memory during a first clock cycle and the associated cache directory is read to determine whether the corresponding main storage address is mapped into the cache memory. If so, and if no status bits in the data word require update, the store to the cache memory is complete. If a different main storage address is mapped into the cache memory, processor logic generates a processor interrupt signal during the second clock cycle, and the processor is interrupted during the third clock cycle while the cache directory is modified to purge the corresponding cache line. If the main storage address is in the cache memory but the data includes at least one status bit requiring update, the interrupt signal is generated during the second clock cycle, with the cache directory modified to update status bits during the third clock cycle. Special logic forces modifications to the cache directory if two consecutive store or fetch operations correspond to the same location in main storage.