The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 1993
Filed:
Mar. 22, 1991
Yasuhiro Nakakura, Osaka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
An addition apparatus adds together two numbers while detecting one of a plurality (n) of possible round-off positions and executing round-off at that position simultaneously with adding together the numbers. The apparatus is divided into a plurality of circuit sections. In a first section, two lowest-significance portions of the two numbers are added together in each of n parallel adder circuits while executing round-off processing at respectively different bit positions in each of the adder circuits. In each of subsequent sections, portions of increasing significance of the two input numbers are added together in a first parallel adder to which a '1' state input carry is applied and a second parallel adder in which a '0' state carry is supplied, and in each section, n section carry signals are--generated in accordance with carry outputs produced from the adders of that section and respective section carry signals produced from the preceding section. A control signal for selecting the output sum from one of the parallel adders of the lowest-significance section and thereby determining the round-off position is generated based on a combination of carry signals supplied to the highest-significance circuit section and MSB signals produced from the two parallel adders of that section.