The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 1993
Filed:
Jul. 10, 1992
Applicant:
Inventors:
Allen Lyu, Milpitas, CA (US);
Charles Stearns, San Jose, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364748 ; 364754 ;
Abstract
A pipelined floating point multiplier is disclosed having the capability of interleaving floating point multiplication with iterative floating point operations (calculations), such as division and square-root taking, by making use of idle stages (pipeline bubbles). This is accomplished with minimal additional circuitry over that required for conventional floating-point multipliers, and does not adversely affect the speed of iterative calculations. Method and apparatus are disclosed.
Lyu, Allen. (1993). Interleaving operations in a floating-point numeric processor (U.S. Patent No. 5204829). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5204829
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