Method for generating power-up pulse

Abstract

In one embodiment, the pulse-generating circuit includes a triggering field-effect device having a source-drain path connected between a voltage supply and an internal node and having a gate connected to a source of reference potential, a capacitor connected between the voltage supply and the output node, and a detector field-effect device having a source-drain path connected between the output node and the source of reference potential and having a gate connected to the internal node. An optional load device, an optional pull-down device, an optional second capacitor, a optional string of diode-connected devices, and an optional feedback device may be included. Device channel lengths are specified for proper operation. In one embodiment, the circuit includes only a detector field-effect transistor and a load field-effect transistor, the detector transistor having a channel length substantially longer than the channel length of the load transistor. The circuit described and claimed herein is immune to the unpredictable behavior of static logic gates during the initial part of the power-on transient when the supply voltage is less than the threshold voltage of the integrated circuit transistors. In particular, the circuit does not have a node connected to both a static pull-up path and a static pull-down path, both of which are on at the same time, forming a linear circuit.