Frequency divider which has a variable length first cycle by changing a

Abstract

A frequency division scheme which offsets for a phase lag produced on initial power-on is described. A division ratio of a programmable counter is initially set at a first division ratio at the time of releasing the programmable counter from its reset state. When the first division cycle is complete, the division ratio is reset to its steady state value. Thus, a delay equivalent to the phase lag is produced. A frequency synthesizer is also proposed where the division ratio is set, and a phase difference is detected. Reset signals are continually set while the phase difference is changed. This cycle is continued until the phase difference is reduced to one cycle of the input signals or less.