The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 1993
Filed:
May. 08, 1990
Koji Eguchi, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A wiring connection structure for a semiconductor integrated circuit device interconnects a plurality of wiring layers isolated by an insulating layer, via a through hole defined in the insulating layer. The wiring connection structure comprises a semiconductor substrate, a first insulating layer, a first wiring layer, a second insulating layer and a second wiring layer. The first insulating layer is formed on a main surface of the semiconductor substrate. The first wiring layer is formed on the first insulating layer. The second insulating layer is formed on the first wiring layer. The through hole is formed in the second insulating layer so as to extend to a surface of the first wiring layer. The second wiring layer is formed on the second insulating layer and connected to the first wiring layer via the through hole. The through hole is a single through hole formed in a region where the second wiring layer overlaps with the first wiring layer. The through hole has a cross section comprising a figure formed by indenting peripheries of a single rectangular figure. This cross section has a longer perimeter than the single rectangular figure. Alternatively, the cross section comprises a figure formed by interconnecting band portions extending along the second wiring layer. A reduction is achieved in components of resistance over an entire through hole forming region. Concentration of current density on side walls of the through hole is also mitigated.