The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 1993

Filed:

Nov. 15, 1991
Applicant:
Inventors:

Jeong-Hyeok Choi, Seoul, KR;

Chul-Ho Shin, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 52 ; 437 45 ; 437 48 ;
Abstract

A method for manufacturing highly integrated NAND and NOR logic mask read only memory (MROM) devices is disclosed. Over the top surface of a semiconductor substrate, where a first polysilicon layer is formed, a pattern of a gate electrode is formed along a word line in the order of odd numbers or even numbers. Next, an insulation layer having a thickness of a submicron range is formed over the top surface of the substrate. And then a photoresist is covered and an etch back process is performed. Thereafter, the exposed insulation layer caused by the etch back process and the polysilicon layer are selectively etched to form a word line spacing corresponding to a thickness of the insulation layer. Thus, spacing between adjacent word lines can be minimized and a process margin can be sufficiently ensured.


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