The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 1993
Filed:
Oct. 15, 1991
Andreas G Papaliolios, Sunnyvale, CA (US);
National Semiconductor, Santa Clara, CA (US);
Abstract
A ferroelectric programming cell utilizable for providing programming signals for configurable logic elements. A preferred embodiment of the ferroelectric programming cell includes a volatile memory cell having first and second internal data storage nodes that are latched in complementary states when the volatile memory cells positive power input is held to a maximum allowed voltage level and its negative power input is held at ground. A node enabling switching means connected between an external signal generator and the volatile memory cell enables an external signal generator to set the values of the first and second complementary internal nodes. First and second substantially identical capacitance-dividers each include a first ferroelectric capacitance means for storing a non-volatile configuration state. Each ferroelectric capacitance means has a driving terminal connected to the external signal generator and a measurement terminal connected to a second capacitance means that enables the volatile memory cell to measure the non-volatile configuration state of the first ferroelectric capacitance means. It also includes a measurement clearing switching means for enabling the external signal generator to force the voltage at the measurement terminal to ground. First and second substantially identical loading switches enable the external signal generator to transfer the nonvolatile configuration state stored in the first and second capacitance dividers to the internal nodes of the volatile memory cell.