The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 1993
Filed:
Jun. 26, 1992
Mark D McDonald, Fremont, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A circuit of use as a multiplier or a logic cell and suitable for low voltage operation. At least three differential transistor stages are used, with two of the stages receiving one input signal, such as a data input signal if the circuit is to function as a logic cell and a multiplicand if the circuit is to function as a multiplier. A load is provided for the two stages which is connected to one of the circuit supply voltages. The third differential transistor stage receives a second input signal which is the other multiplicand if the circuit is configured as a multiplier and which is a clock signal if the circuit is configured as a logic cell. Circuitry is provided for controlling current flow through the first and second stages in response to current flow in the third stage. If the circuit is configured as a multiplier, the change in current flow in the first and second stages caused the transconductance of the stages to change so that multiplying action will take place. If the circuit is configured as a logic cell, the change is current flow due to the transitions in the clock causes the first stage to be active so that the data input is first transferred to that stage. Further transitions in the clock then cause the first stage to be inactive and the second stage active so that the data is transferred from the first to the second stage and stored in the second stage. The circuit architecture permits low voltage operation such as needed in battery powered applications.