The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 1993

Filed:

Dec. 19, 1990
Applicant:
Inventor:

Chai-Chin Chao, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307475 ; 307451 ; 307456 ; 307443 ;
Abstract

Generally, and in one form of the invention, a circuit is provided with a terminal 50 to receive an input signal which is applied to the input of an inverter 100 which is responsive to TTL level signals and which exhibits hysteresis. The output of inverter 100 is connected to two inverter chains. The first inverter chain 110, 112, 114 is comprised of an odd number of inverters and produces a first output at terminal 62 which represents a 'true' version of the input signal. The second inverter chain 102, 104, 106, 108 is comprised of an even (or zero) number of inverters and produces a second output at terminal 60 which represents a 'complement' version of the input signal.


Find Patent Forward Citations

Chao, Chai-Chin. (1993). Ttl compatible hysteresis input buffer with improvable ac margin (U.S. Patent No. 5194767). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5194767

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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