The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 1993
Filed:
Nov. 13, 1991
Mitsutoshi Sugawara, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A multi-level logic input circuit is composed of a first and a second resistor, a first polarity current mirror circuit whose input is connected to the first resistor and which has a plurality of output nodes, and a second polarity current mirror circuit whose input is connected to the second resistor and which has a plurality of output nodes. The output nodes of the first polarity current mirror circuit are connected correspondingly with the output nodes of the second polarity current mirror circuit. The output nodes are led out as a plurality of output terminals. At least one of the output nodes of each of the current mirror circuits has a current ratio different from that in all the remaining output nodes thereof. The multi-level logic input circuit is simple in its configuration, and it enables to realize multi-level inputs with small current consumption.