Clock control circuit for suppressing clock pulses

Abstract

In a clock control circuit for suppressing a clock pulse in a plurality of devices which operate in synchronization with each other, the clock control circuit detects first and second clock suppress conditions, generates a first clock suppress signal in all the devices based on the detection of the first clock suppress condition, generates a second clock suppress signal in a particular device based on the detection of the first or second clock suppress conditions, transmits the clock suppress signals to all the devices, and suppresses the clock pulse in all the devices based on the first and second clock suppress signals. The second clock suppress signal suppresses the clock pulse after it is suppressed by the first clock suppress signal, and continues to suppress the clock pulse until a suppression release signal is received.