The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 1993
Filed:
Apr. 20, 1992
G Jack Lipovski, Austin, TX (US);
Board of Regents, The University of Texas System, Austin, TX (US);
Abstract
An apparatus and method for synchronizing parallel processors utilizing a lookahead synchronization circuit is provided by the present invention. A five gate logic circuit is formed as a cell and this cell can serve as a node in a tree logic operation circuit. The tree is capable of realizing a variety of fetch-and-operation, priority and operation-and-broadcast primitives and the cell can serve in a carry circuit of a binary adder. The tree may be pruned at any point and the circuit will continue to function for those nodes remaining in the tree. Processing elements are attached to leaf nodes of the tree. The present invention is capable of realizing the fetch-and-exclusive-OR, fetch-and-add, fetch-and-AND, fetch-and-OR, fixed priority schema, round-robin priority schema, hogging priority schema, swap, data exchange, broadcast, shift-function, broadcast-from-the-root, AND-and-broadcast, OR-and-broadcast, minimum-and-broadcast, maximum-and-broadcast, exclusive-OR-and-broadcast, fetch-and-minimum, and fetch-and-maximum primitives. The circuit affords significant power in synchronizing parallel processors utilizing simple cells configured in a tree structure.