Semiconductor memory having a plurality of ports

Abstract

This invention discloses a static random access memory having a plurality of data writing/reading ports, including a pair of bit lines of a first port and a pair of bit lines of second port, a memory cell for storing and outputting data, a bit line sense amplifier for sensing and amplifying data from the memory cell, a first transfer gate arranged between a first node of the memory cell and a first bit line of the first port, a second transfer gate arranged between a second node of the memory cell and the second bit line of the first port, a third transfer gate arranged between the first node of the memory cell and the first bit line of the second port, and a fourth transfer gate arranged between the second node of the memory cell and the second bit line of the second port, a drain source transconductance of the third and fourth transfer gates being larger than a drain-source transconductance of the first and second transfer gates, first and second base ground circuits, arranged between the bit line sense amplifier of the first port and the first bit line and between the bit line sense amplifier of the first port and the second bit line, for clamping a potential of each of the first pair of bit lines to a predetermined level upon start of a read operation of data.