Pulse width detecting circuit and pll synthesizer circuit using the same

Abstract

A PLL synthesizer circuit includes a reference frequency generator for generating a reference frequency signal and a reference clock signal, a phase comparator for comparing a phase of the reference frequency signal with an output signal and for outputting a phase difference signal having a pulse form, and a voltage-controlled oscillation device for generating the output signal having a frequency dependent on the phase difference signal. The PLL synthesizer circuit also includes a phase lock detecting circuit for determining whether or not the phase difference signal has a pulse width in which the reference clock signal successively changes n times (n is numeral equal to or greater than 2) and for outputting a phase lock detection signal representing that the PLL synthesizer circuit is in a phase-locked state when it is determined that the reference clock signal does not successively change n times in the pulse width of the phase difference signal. There is also provided a pulse width detecting circuit suitable for application of a phase lock/unlock detection in a PLL synthesizer.