The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 1993
Filed:
Sep. 23, 1991
Geoffrey S Gongwer, San Jose, CA (US);
Atmel Corporation, San Jose, CA (US);
Abstract
A programmable logic device having multiple first logic arrays, such as AND arrays, each with a different set of inputs and all simultaneously operating, in which the outputs from two or more first logic arrays are shared in a single speed logic gate or array, such as an OR gate or array. In one embodiment, there are N first logic arrays and M second logic arrays connected such that each second logic array receives intermediate terms from every first logic array and intermediate terms from each first logic array are shared by plural second logic arrays. In a second embodiment, there are N first logic arrays and a plurality of second logic gates connected so that at least some of the second logic gates receive intermediate terms from two adjacent first logic arrays.