Pipelined signal processor having a plurality of bidirectional

Abstract

A signal processor comprising a split pipelined parallel processor which processes data signals from external signal sources and provides signal processing functions utilizing a plurality of data formats. The signal processor comprises an external interface unit having a serial control port and a plurality of bidirectional parallel ports. The interface unit transfers control and data signals between the signal processor and external devices. The parallel ports are configurable as individual parallel ports or coupled pairs which form a port having the combined data path of the two coupled ports. An arithmetic element controller comprising a microprogram memory and a control program memory is coupled to the interface unit which loads applications programs into the control program memory and executes the programs. The arithmetic element controller controls the processing of control and data signals in the signal processor. A plurality of pipelined arithmetic elements are coupled to the arithmetic element controller, each comprising a data store memory, a multiplier and a register and arithmetic logic unit. Each arithmetic element has its data store memory coupled to the external interface unit to receive and store data signals, and to its multiplier and the register and arithmetic logic unit in order to perform fixed and floating point arithmetic operations on the data stored in the data store memory. These arithmetic operations are performed in accordance with application program and microprogram instructions contained in the control program and the microprogram memories. The persent invention provides for a high performance architecture for use with vector and matrix signal processing algorithms that minimizes the amount of hardward needed to implement them.