The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 1993
Filed:
May. 21, 1990
Takahiko Kozaki, Koganei, JP;
Kenichi Asano, Akishima, JP;
Mineo Ogino, Hanno, JP;
Eiichi Amada, Tokyo, JP;
Noboru Endo, Freehold, NJ (US);
Yoshito Sakurai, Yokohama, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi VLSI Engineering Corporation, Tokyo, JP;
Link Laboratory Inc., Tokyo, JP;
Abstract
A switching system exchanges communication information as fixed length cells between a plurality of incoming and outgoing highways. The fixed length cells each have a plurality of data portions with one data portion designated as a header portion for containing switching information. An address generating circuit generates read addresses and write addresses in response to the header portion of each cell and a control circuit. The plurality of cells from the incoming highways are simultaneously rotated in a rotation matrix with each of the cell's data portions rotated to a unique internal path. The data portions are then transmitted to identical write addresses in a plurality of memories via delay circuitry. The write addresses are transmitted through shift registers to the plurality of memories to allow the data portions of a single cell to occupy identical addresses within a plurality of memories. The control circuitry determines the correct outgoing highway for each cell based upon information contained within the header portion of each cell or a routing table. The data portions are then read out of read addresses in the plurality of memories and rotated by another rotation matrix. The rotated data portions reform the fixed length cell along a determined outgoing highway.