The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 02, 1993

Filed:

Nov. 08, 1991
Applicant:
Inventors:

Shinobu Aoki, Kariya, JP;

Haruo Takagi, Kariya, JP;

Takanori Okabe, Kariya, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257266 ; 257264 ;
Abstract

A static induction transistor has a gate region formed with a protrusion extending toward a drain region. The protrusion is located toward one side of the gate region such that a shallower gate region lies between the protrusion and the nearest source region. When a reverse voltage higher than the withstand voltage is applied between the gate and drain, avalanche breakdown occurs only in a region immediately below the protrusion, and no hot carriers are allowed to flow into a source region. Deterioration of the voltage-withstanding property and destruction of the device is thereby prevented. Another embodiment has a semiconductor region of a first conductivity type formed in a peripheral portion of a semiconductor layer of the first conductivity type in which a plurality of gate regions are disposed and adjacent a first major surface thereof. The distance between the semiconductor region and the nearest gate region is less than the distance between gate and drain regions such that the withstand voltage between the semiconductor region and the nearest gate region is less than that between the gate region and drain region. When a reverse bias voltage higher than a withstand voltage is applied between the gate and drain, the avalanche breakdown occurs only between the semiconductor region and the gate region nearest thereto.


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