Multi-stage a/d converter

Abstract

An analog-to-digital converter (ADC) having two cascaded A/D stages of the parallel type wherein the analog signal is compared with a set of threshold reference voltages. The first stage develops a set of most-significant bits and produces two analog residue signals: a normal residue corresponding to the difference between the analog input and the threshold voltage below the analog input, and a second residue corresponding to the difference between the analog input and the threshold voltage above the analog signal level. These two residue signals are amplified and directed to the second A/D stage. The sum of the residue signals equals one LSB of the first A/D stage, so that the two residues supply to the second stage information about the quantization error of the previous stage as well as the quantization step size to be used to define full-scale at the second stage. The second A/D stage includes a parallel converter for developing a set of less-significant bits representing the ratio of the normal residue signal to the sum of the two residue signals. The most-significant and less-significant sets of bits are combined to provide the final digital output. Errors due to inaccuracies in interstage gain are reduced due to the use of two residue signals for generating the less-significant bits.