The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 1993
Filed:
Oct. 20, 1989
Honeywell Bull Italia S.p.A., Caluso, IT;
Abstract
In a data processing multiprocessor system having distributed shared resources where each system processor (7) is provided with at least a local memory (8) to which it get access through a local bus (11), and with an interface unit (10) for connection of the local bus (11) to a system bus (5) and wherein each of the system processors may have access the local memory of another processor through its own local bus, its own interface unit, the system bus and the local bus of the other processor, deadlock is prevented by providing a bypass unit (40) of the interface unit (10) for enabling access from the system bus to the local bus through the bypass unit, a block (9) connected between the local bus and the interface unit (10) for latching system bus access requests received from an agent processor on the local bus, and a block (12) for isolation of the agent processor outputs from local bus, so that each agent processor may post read/write operations in the related latching block (9) for latching bus access requests and thereafter release its own local bus without awaiting completion of the operation, whereby the local bus is available to receive access requests received from the system bus through the bypass unit (40), the operation pending in the latching block (9) being completed, if a read operation, by reconnection of the agent processor (7) and the latching block (9) to the local bus.