The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 26, 1993
Filed:
Oct. 24, 1991
Matthew M Nowak, San Diego, CA (US);
Roland D Rothenberger, Poway, CA (US);
Mark A Vinson, San Diego, CA (US);
Unisys Corporation, Blue Bell, PA (US);
Abstract
An integrated circuit die contains a total of at least 10,000 bipolar logica cells that dissipate at least 75 watts of power. To supply such a large amount of power to the logic cells, thin sputtered power busses of 3 .mu.m thickness overlie the logic cells; an insulating layer surrounds the power busses; openings in the insulating layer defined plating regions on the power busses; an electroplating base film lies throughout the plating regions; and, a thick plated conductor, of at least 16 .mu.m thickness, lies on the electroplating base film. By supplying power to the bipolar logic cells via the composite structure of the thin power busses and thick plated conductors, a noise margin problem in the logic cell output signals is avoided. With 16 .mu.m thick plated conductors, the total number of logic cells on the die can be increased until their total power dissipation reaches 75 watts. With 21 .mu.m thick plated conductors, total die power can be increased to 100 watts.