Logic circuit with bipolar cmos configuration

Abstract

A logic circuit has a logic circuit portion which includes a first MOS transistor circuit, a second MOS transistor circuit and a third MOS transistor circuit for conducting a logical operation. The logic circuit also has a first and a second bipolar transistor for driving a next stage logic circuit and an N-channel MOS transistor for discharging the charge in the base of the second bipolar transistor. There is provided an inverter circuit whose input terminal is connected either to the output terminal or the base of the first bipolar transistor. An input to the gate of the N-channel MOS transistor is supplied from the output terminal of the inverter circuit so that, when the output changes from its high level to its low level, there is no possiblity for the first and second bipolar transistors to turn to their ON-state at the same time. Consequently, all of the current which is to be supplied from the third MOS transistor circuit to the base of the second bipolar transistor flows thereto without by-passing and, as a result, there is no reduction in the collector current of the second bipolar transistor. Thus, it is possible to have the load capacitance at the next stage discharged at a high speed and hence to have the circuit operate at a high speed.