The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 1993

Filed:

Nov. 05, 1991
Applicant:
Inventor:

David A Willems, Salem, VA (US);

Assignee:

ITT Corporation, New York, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03H / ;
U.S. Cl.
CPC ...
333164 ; 333103 ; 307571 ;
Abstract

A reflection-type phase shifter employs an artificial delay line which is constructed of high impedance transmission line sections for the series inductive elements in the transmission line. Each junction between inductances in the transmission line is associated with a separate FET pair. The FET pair includes a first FET having the source to drain path coupled between the junction and a point of reference potential. The gate electrode of the first FET is coupled via the source to drain path of a second FET to the point of reference potential. The gate electrode of the second FET is coupled to one terminal of a resistor which is of a larger value compared to the ON resistance of the FET. This resistor has another terminal coupled to a control voltage source. Each junction or tap between inductors is returned to ground through an additional circuit where the gate electrode of the second FET in each circuit is coupled to that resistor which is also coupled to the gate electrode of each first FET in the FET pair. In this manner, when a given FET is selected and biased ON to implement a given length line, each FET device which is further down the chain is also operated, based on the cascade arrangement of FETs. In circuit operation, each FET which is further down the chain automatically conducts due to the difference in the ON resistance of the FET as compared to the value of the above-noted resistor. The circuit eliminates the need for complex digital control by automatically switching all the FETs ON between the FET selected and the shorted end of the transmission line.


Find Patent Forward Citations

Loading…