Threaded interpretive data processor

Abstract

A threaded interpretive processor includes an input/output (I/O) bus (10) and an address bus (12) for carrying data thereon. An internal ROM/RAM (80) is interfaced with the I/O bus (10) and is addressable from the address bus (12). Instructions placed on the I/O bus (10) are clocked onto the address bus (12) through an instruction pointer (86) in response to a system clock (26). The data on the I/O bus (10) is also clocked to a microcode ROM (60) through an instruction register (58). The microcode ROM (60) outputs microcode instructions to control the system operation. The microcode instructions control a parameter stack (18). The parameter stack (18) consists of an eight register rotary stack (44) that has the outputs thereof simultaneously addressable by two output buses (46) and (48) and the inputs thereof addressable by an interface bus (36) and a data input bus (50). The outputs of the rotary stack (44) are input to an arithmetic logic unit (16), the output of which is input back into the rotary stack (44). Transfer gates are provided to control data flow on the output buses and input buses such that the data in the rotary stack (44) can be manipulated. Addresses of microcode instructions are sequentially placed onto the I/O bus (10) for controlling the microcode ROM (60) and the instruction pointer (86) increments this instruction address to select the next sequential instruction address. In this manner, instructions can be sequentially executed in sequential clock cycles.