Generator detecting internal and external ready signals for generating a

Abstract

In a debugging microprocessor having a function of elongating a bus cycle in response to an external ready signal and used in a microprocessor development support system having a function capable of tracing and analyzing the result of execution, there is provided a generator for generating a bus cycle end signal for the microprocessor development support system. The generator comprises a ready detection circuit receiving an external ready signal, a clock signal and an enable signal which is rendered active only when the debugging microprocessor is in a condition capable of accepting data. The ready detection circuit operates to detect the status of the external ready signal at a time defined by a clock appearing when the enable signal is active, so as to generate an internal ready signal if the external ready signal is active. A control circuit is connected to receive the internal ready signal for generating a signal indicative of an end of the bus cycle for a predetermined period of time starting from a next clock state. This bus cycle end signal is outputted to an external device or stage of the debugging microprocessor.