High resolution symmetrical divider circuit

Abstract

A method divides a recurrent digital clocking signal into a quotient digital signal having a substantially symmetrical duty cycle within a range of programmable quotients, the quotients being selectable in single increments of the recurrent digital clocking signal within a range as selected by a divisor. The method includes the steps of loading the divisor from a source into a down counter clocked by the recurrent digital clocking signal; down counting from the divisor to zero with the down counter in synchronism with the recurrent digital clocking signal; setting a bistable latch to a first state of synchronism with a beginning of down counting from the divisor, the bistable latch for putting out the quotient digital signal; dividing the divisor by two to provide a half-count value; comparing the half-count value with a count reached by the down counter and generating a compare true signal upon detected equivalence of the half-count value and the count reached; and, setting the bistable latch to a second state opposite the first state in synchronism with the compare true signal. As one aspect of this invention the foregoing steps are continuously repeated every time the step of down counting reaches zero.