The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 1992

Filed:

May. 15, 1991
Applicant:
Inventors:

Hisaki Hiraiwa, Kanagawa, JP;

Mitsuhiro Suzuki, Tokyo, JP;

Takushi Kunihiro, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03H / ;
U.S. Cl.
CPC ...
375 12 ; 375118 ; 375 14 ;
Abstract

The present invention relates to an equalizing system in which an input signal is supplied to a series circuit of a plurality of delay means, the input signal and delayed output signals of the respective delay means are multiplied with coefficients and multiplied outputs are added to thereby produce an equalized output signal. In this equalizing system, the input signal is supplied to the series circuit of the plurality of delay means so that the input signal is transmitted in the positive direction within the series circuit so as to be sequentially delayed, the input signal is then transmitted in the reverse direction within the series circuit so as to be sequentially delayed, the input signal is transmitted again in the positive direction within the series circuit so as to be sequentially delayed, an amplitude error of the output equalized signal is detected, and coefficients multiplied with the delayed output signals of the respective delay means are calculated in response to the detected amplitude error so that the amplitude error is minimized.


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