The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 1992

Filed:

Aug. 14, 1991
Applicant:
Inventors:

Masahiro Ueda, Hyogo, JP;

Toshiaki Hanibuchi, Hyogo, JP;

Katsushi Asahina, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307475 ; 307455 ; 307456 ;
Abstract

A level conversion apparatus for converting a signal of an ECL level into a signal of a TTL level is disclosed which has source voltages set to a potential corresponding to a lower limit logic swing of the ECL level and a potential corresponding to an upper limit logic swing of the TTL level. This level conversion apparatus includes a reference voltage generating circuit for generating an upper limit reference voltage and a lower limit reference voltage divided from a voltage applied between a source terminal Vcc and a ground terminal, a control signal generating circuit for generating a control signal in response to the ECL level signal, determined by a difference between the upper limit reference voltage and the lower limit reference voltage, and an output switching circuit for carrying out a switching operation in response to the controlled signal. The output switching circuit outputs a signal determined by the potential corresponding to the upper limit logic swing of the TTL level and a ground source.


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