The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 1992
Filed:
Jan. 31, 1990
Applicant:
Inventors:
Hiroyuki Watanabe, Tokyo, JP;
Chikahiro Hori, Yokohama, JP;
Assignee:
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; H03K / ;
U.S. Cl.
CPC ...
364491 ; 364490 ; 307480 ; 3074821 ;
Abstract
In designing an integrated circuit having a logic circuit area and a clock supplying circuit, the layout of the clock supplying circuit can be designed before the completion of the layout designing of the logic circuit area. Clock buffers and wires that are component elements of the clock supplying circuit are arranged in a peripheral region of the logic circuit area. This arrangement enables the layout designing of the clock supplying circuit to be done with no influence of the layout designing of the logic circuit area.