Data processor having a deferred cache load

Abstract

A data processing system is provided having a secondary cache for performing a deferred cache load. The data processing system has a pipelined integer unit which uses an instruction prefetch unit (IPU) to maintain a steady stream of instructions to the pipeline. The (IPU) issues prefetch requests to a cache controller on a cache half-line basis. In conjunction with the prefetch request, the IPU transfers a prefetch address to a cache address memory management unit (CAMMU), for translation into a corresponding physical address. The physical address is compared with the indexed entries in a primary cache, and compared with the physical address corresponding to the single cache line stored in the secondary cache. When a prefetch miss occurs in both the primary and the secondary cache, the cache controller issues a bus transfer request to retrieve the requested cache line from an external memory. While a bus controller performs the bus transfer, the cache controller loads the primary cache with the cache line currently stored in the secondary cache. Thus, the deferred loading of the primary cache, after the prefetch miss, does not stall subsequent prefetches from the integer unit.