Preset number of pulses generated within given time period even when

Abstract

A circuit arrangement generates a preset number of output pulses each time between two consecutive input pulses, the distance between the input pulses being subject to variation. The output pulses should be approximately evenly distributed, which even distribution, however, cannot be maintained when the cycle of the input pulses changes. To achieve first and foremost that the total number of output pulses is reached as quickly as possible in the case of a change in the input pulse cycle, the circuit includes a first counter device, which supplies a measure for the cycle duration of the input pulses in relation to a clock pulse, and this measure is used as a preset value for the next cycle for a further counter, which counts down the preset value in period with the clock pulses. The carry pulses of the further counter essentially indicate the output pulses, the number thereof is counted in each cycle by means of a third counter, which ends the further generation in the relevant cycle after the preset number has been reached, while in the case of a shortening of the input pulse cycle, any deficiency in the number of generated pulses is additionally inserted in the next cycle. As a result, the total number of the output pulses is made equal to the preset number in the shortest possible time, albeit to the detriment of an even distribution.