The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 1992
Filed:
Dec. 06, 1990
Kazuhiro Yoshimura, Kawasaki, JP;
Shuichi Suzuki, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A field effect transistor includes a semiconductor substrate having a first conduction type and functioning as a drain of the field effect transistor, and a back gate region formed in the semiconductor substrate and having a second conduction type opposite to the first conduction type. The field effect transistor also includes a source region formed in the back gate region and having the first conduction type, an insulator film formed on the semiconductor substrate and having first and second windows, and a gate electrode covered by the insulator film and located so that a channel is formed in the back gate region. Further, the field effect transistor includes a guard region formed in the semiconductor substrate and located close to the back gate region. The guard region has the second conduction type, and has a first portion located on a first side of the guard region facing the back gate region and a second portion located on a second side opposite to the first side. A first breakdown voltage obtained at a first junction between the second portion and the semiconductor substrate is lower than that obtained at a second junction between the back gate region and the semiconductor substrate. Furthermore, the field effect transistor includes an electrode formed on the insulator film and connecting the guard region and the back gate region via the first and second windows.