Microprocessor system private split cache tag stores with the system tag

Abstract

The computer system architecture utilizes the ability to actively force a ghost line state in management of a split instruction and operand cache associated with an instruction unit with respect to a secondary system integrity cache tag store separately managed by a system controller. The split instruction and operand cache and the system controller tag store permit the management of multiple copies (line-pairs) of a memory line by storing address tag line pair state information with respect to each memory line present in the split-cache to allow determinations of whether and where the respective memory line pair members reside upon access of any one member. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair. A ghost line state is forced whenever a modified memory line, existing as a member of a line pair is to be stored into the operand cache and a concurrent storage of the modified memory line in the instruction cache cannot be performed.