Spike filtering circuit for logic signals

Abstract

A spike filtering circuit for a logic signal comprises a signal transfer circuit formed by a first transfer gate followed by a pair of inverters, functionally connected in series between the input terminal and the output terminal of the circuit and a second transfer gate connected between the output terminal and the input node of the first of said two inverters. The two transfer gates are driven in phase opposition to each other by means of a pair of control signals in phase opposition to each other which are generated by a control circuit functioning in a feedback mode. Basically the control circuit is formed by an exclusive-OR gate having two inputs connected to the output terminal of the circuit directly and through a delay network, respectively. Through an output node of the exclusive-OR gate is produced a first control signal from which the pair of control signals in phase opposition to each other are derived by means of inverting stages. The delay network introduces a delay after a transition of the signal on the output terminal of the circuit has occurred during which said first transfer gate is momentarily disabled and said second transfer gate is enabled in order to maintain on the output terminal the state reached with the first transition for a period of time sufficiently long to allow the decay of spikes which may be been generated by said transition of the logic signal. By employing a NAND gate and an inverter connected in cascade to the output of said exclusive-OR gate, the filtering circuit may be initialled by applying an enabling signal to a second input of said NAND gate.