The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 1992

Filed:

Feb. 26, 1991
Applicant:
Inventors:

Gerard J Shaw, San Jose, CA (US);

Jok Y Go, Santa Clara, CA (US);

Jay H Chun, Fremont, CA (US);

Bruce G Armstrong, Belmont, CA (US);

Jerry W Drake, Los Gatos, CA (US);

Assignee:

Raytheon Company, Lexington, MA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
365105 ; 365 96 ; 365163 ; 257476 ; 257530 ;
Abstract

A memory cell comprising a memory region of amorphous silicon, such memory region having a first state of substantial electrical nonconductivity programmable to a second state of substantial electrical conductivity in response to an electrical programming signal applied thereto. The memory region is disposed over a metal Schottky contact, such as platinum-silicide (PtSi), formed in a support body. A first barrier layer comprising a refractory metal such as titanium-tungsten (TiW) is disposed between the memory region and Schottky contact. A first input terminal comprising a metal strip conductor, such as aluminum, is disposed over the memory region, with a second refractory metal barrier layer being disposed between the memory region and metal strip conductor. A second input terminal is disposed within the support body. With such arrangement, the material of the Schottky contact (PtSi) is substantially prevented from migrating or diffusing into the silicon memory region upon application of the electrical programming signal between the first and second input terminals, thereby preserving the structure of the metal contact and maintaining a low reverse bias leakage current for a Schottky diode comprising such metal contact. Also, the level of the programming signal may be increased, providing more complete programming of the memory region to the second, electrically conductive state.


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