Nrz clock and data recovery system employing phase lock loop

Abstract

An improved NRZ clock and data recovery system lends itself to integration, includes a NRZ phase detector, an NRZ frequency detector and a lock detector, and provides automatic centering of the clock edge within the bit interval in a manner that is independent of analog delays and process and temperature variations. NRZ data is applied to one side of an exclusive-OR gate and a twice delayed version of the NRZ data is applied to the other side. The output of the XOR gate, a 'blivet' signal, is applied to a NRZ phase detector comprising two AND gates, one of which has as its other input a recovered clock signal output of a VCO and the other of which has as its other input an inverted version of the recovered clock signal. The 'up' and 'down' outputs of the AND gates indicate which direction a frequency control signal should change the VCO frequency. A data holding flip-flop whose input is a once delayed version of the NRZ data is clocked with the recovered clock signal. The NRZ frequency detector monitors the state of the recovered clock signal on opposite edges of the blivet to detect too-high, too low and good conditions. The results of the detection can be ignored if a lock signal indicates that the phase lock loop is locked. The lock detector consists of a saturating up/down counter that is incremented by one when good blivets occur and is decremented by four when not-good blivets occur.