Integrated sample and hold circuit with feedback circuit to increase

Abstract

An integrated sample and hold circuit includes a capacitor that is charged through a channel, such as a first input transistor's channel. Feedback circuitry connected to the first transistor's channel leads maintains approximately zero voltage difference between the channel leads to prevent leakage current when the first transitor is turned off. Isolation circuitry, such as a second input transistor, isolates the first transistor from the input voltage while a voltage level is being stored, and the gates of both input transistors can be connected to receive the same store signal. The feedback circuitry can include a follower transistor with its gate connected to the first transistor's output lead and a first channel lead connected to the first transistor's input lead and to load circuitry that maintains current flow through the follower transistor. To ensure that it does not pass current to or from the capacitive element, the follower transistor can be an MOS device or other insulated gate transistor. The follower transistor's other channel lead can be connected to a bias voltage that, together with the current flow, keeps the follower transistor's gate and first channel lead at the stored voltage level. The load circuitry can include a transistor identical to the follower transistor, with one of its channel leads connected to the follower transistor's first channel lead and with its other channel lead and its gate lead connected to a bias voltage that maintains sufficient current flow through the follower transistor. The substrate can be an insulating material such as glass, quartz, sapphire, silicon dioxide, or silicon nitride, and the circuitry can be thin film structures, amorphous silicon, polysilicon, or single crystal devices, so that the only significant leakage path to and from the capacitive element is through the first input transistor's channel.