The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 1992
Filed:
Mar. 30, 1992
Juergen A Foerstner, Mesa, AZ (US);
Bor-Yuan Hwang, Tempe, AZ (US);
John E Schmiesing, Tempe, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A method for fabricating BiCMOS on SOI. An SOI wafer (14) with an oxide layer (17) and a nitride layer (16) has areas isolated by a LOCOS or mesa isolation (13). A region (15) is defined for CMOS structures from which the insulating layers (17,16) are removed. A gate oxide (21), a polycrystalline silicon layer (22), and a second insulating layer (23,24) is formed. A region for emitters (26) is defined and nitride deposited to form a spacer (27). An oxide layer (28) is grown over the polycrystalline silicon (22) within the emitter region (26). The wafer (14) is etched to the underlying monocrystalline silicon (18) forming base contacts (31). A polycrystalline silicon spacer (36) is formed from a second polycrystalline layer (43) and an oxide spacer (40) is deposited. A region for bipolar collectors (32) and CMOS areas (34) is defined and a spacer (38) deposited.