The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 1992
Filed:
Nov. 29, 1990
Lanny L Lewyn, Laguna Beach, CA (US);
Brooktree Corporation, San Diego, CA (US);
Abstract
A first switch (e.g. semiconductor) becomes conductive when at least one of two binary inputs to be added is a binary '1'. A second switch (e.g. semiconductor) becomes conductive when there is a carry of a binary '1' from a preceding stage. The semiconductors provide a particular potential on an output line when both semiconductors are conductive. This potential provides a binary carry to a carry switch in the next stage. The carry switch in the next stage is an n-channel semiconductor when the carry switch in the previous stage is a p-channel semiconductor. A logical network also produces a signal when both of the binary inputs are a binary '1'. This signal causes a third switch (e.g. semiconductor) to become conductive and to produce the particular voltage on the output line whether or not the particular voltage is produced on the output line by the operation of the first and second switches. The voltage on the output line is thereafter reset to a second particular value by a reset signal from a fourth switch (e.g. semiconductor). A fifth switch (e.g. semiconductor) also simultaneously receives a reset voltage to reset the common node between the first and second switches to the particular value. The first and second switches in the next state then respectively respond to a binary '1' in at least one of two binary inputs and to the carry output from the preceding stage in the manner described above.