Digital signal processing circuit for carrying out a convolution

Abstract

A digital signal processing circuit has a coefficient storing portion, a computing portion, a coefficient selection control portion and a coefficient transfer portion. The coefficient storing portion stores multiplier coefficients used for a convolution computation, in which a value of each multiplier coefficient can be arbitrarily changed. The computing portion stores a series of input data to be inputted thereto sequentially during certain period to be previously passed, so that the computing portion carries out the convolution computation on the series of input data by use of the multiplier coefficients. In addition, the coefficient selection control portion controls a selection of a data input/output manner, i.e., either a data first-in-first-out manner or a data circulation manner is selected. The coefficient transfer portion inputs the multiplier coefficients to the storing portion from a external device, or outputs the coefficients to the external device. The convolution computation is carried out on the series of input data by use of the multiplier coefficients, which are supplied from the coefficient storing portion or the coefficient transfer portion. Thus, various digital signal processings can be performed so that the large-scale convolution computation can be carried out on the series of input data by use of the multiplier coefficients which can be easily set.