The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 1992

Filed:

May. 12, 1989
Applicant:
Inventors:

Ramon Co, Trabuco Canyon, CA (US);

Kenneth W Ouyang, Huntington Beach, CA (US);

Jui C Liang, Laguna Niguel, CA (US);

Assignee:

Western Digital Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257408 ; 361 56 ; 361 91 ; 257355 ; 257357 ; 257409 ;
Abstract

A field effect transistor device formed on an integrated circuit chip substrate and driven by the on-chip voltages having a well region formed in the substrate, and source and drain regions one of which is formed in the well region. The well region has a lower doping concentration than the source and drain regions and is of the same conductivity type. The well region provides a reduced electric field gradient at the source/substrate or drain/substrate junction and significantly increases the breakdown resistance of the device to DC voltages higher than the on-chip voltages. An input/output protection circuit employing the field effect transistor coupled in series between an integrated circuit output pad and the active devices on the chip providing ability to withstand coupling of the pad to a relatively high DC voltages.


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