The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 1992

Filed:

Aug. 07, 1990
Applicant:
Inventor:

Sajol C Ghoshal, Orangevale, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L / ; H03D / ;
U.S. Cl.
CPC ...
328155 ; 328133 ; 307262 ; 307271 ; 331158 ; 331179 ; 375118 ; 375119 ; 375120 ;
Abstract

A circuit for attenuating phase jitter on an incoming clock signal includes a digitally controlled oscillator, a phase lock loop including a phase detector, and a dithering circuit. The oscillator is capable of generating N discrete frequencies selectable through digitally controlled inputs controlling switched, capacitively-loaded amplifier stages. The phase lock loop provides a total of C.times.N.times.NB frequencies. The phase detector consists primarily of an up/down counter with an overflow/underflow limiter circuit. The dithering circuit modulates the oscillator signal to reduce inadequate rejection behavior when the incoming clock frequency is substantially the same as one of the N selectable frequencies of the oscillator divided down to match the frequency of the incoming clock.


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