The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 1992

Filed:

Jun. 03, 1991
Applicant:
Inventor:

David P Favreau, Allentown, PA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437 31 ; 437 90 ; 437162 ; 437193 ; 148D / ;
Abstract

A polysilicon self-aligned transistor has a polysilicon layer (24) with a cavity (30) formed therein. To form the polysilicon layer (24) with a cavity (30), a thin seed layer (14) is disposed over an epitaxial layer (11a). Dielectric layers (16, 18) are formed over the seed layer (14), and are subsequently etched to define the polysilicon layer (24) and the cavity (30). The cavity (30) is defined by a dielectric plug (22). The exposed seed layer (14) is used to selectively grow the polysilicon layer (24). Thereafter, the dielectric plug (22) is removed to form the cavity (30) through which the base (32) is implanted into the substrate (12) and the emitter (36) is formed.


Find Patent Forward Citations

Favreau, David. (1992). Self-aligned bipolar transistor using selective polysilicon growth (U.S. Patent No. 5162245). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5162245

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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